Single core binary counter



United States Patent O 8 Claims. (Cl. 340-168) assignor to Remingcorporation of Dela The present invention relates to computer devices, and is more particularly concerned with a magnetic counter for use in such devices.

As is well known, one of the basic components of computing systems is the counter device. Such devices have in the past normally been constructed of vacuum tube components and while these in the main are quite reliable, they present a number of disadvantages. The most obvious of these is that inasmuch as vacuum tubes are employed, such tubes are subject to normal failure. Further, they are of relatively fragile construction and may present a serious problem in maintenance of a relatively large computing system. Again, due to the large or relatively large size of these tubes, they present a serious problem in packaging and in other disposition of components within an overall computing system.

Other types of devices have been suggested for use in computing work and for use as counters in such work. Among these is the magnetic amplifier.

It is a prime object of the present invention to utilize a form of magnetic amplifier in the construction of a simple but reliable counter.

A further object of the present invention resides in the provision of a counter device utilizing a magnetic amplifier, which amplifier employs but a single core.

Still another object of the present invention resides in the provision of a highly rugged counter device which can be made in very small sizes.

Still another object of the present invention resides in the provision of a counter which is less expensive to construct than prior art type counters, and which requires 3 practically no maintenance whatsoever.

A still further object of the present invention resides in the provision of a magnetic counter for use in binary digital computer devices, which magnetic counter utilizes only a single core in conjunction with a storage device, such as a capacitor, for effecting the desired counting function.

Still another object of the present invention resides in the provision of a single core binary counter utilizing a magnetic core which preferably exhibits a substantially rectangular hysteresis loop and which core carries but a single coil for effecting both an output and core control.

Still a further object of the present invention resides in the provision of a single core binary counter which, when used in conjunction with a low impedance input source, need not have blocking pulses applied thereto.

In accordance with the several objects of my invention, I provide a single core binary counter which has a core preferably constructed of magnetic material exhibiting a substantially rectangular hysteresis loop. The core carries thereon a single winding, one end of which is coupled to a source of input pulses, and the other end of which is connected to a capacitive or storage device. The operation of the device is such that an input pulse will selectively pass through the said winding to charge the said capacitive device, and this capacitive device in turn discharges at least partly back through the said winding to change the operating point on the hysteresis loop of the said core in preparation for the next input pulse. As a result of the foregoing operation, and as will be described, the counter of the present disclosure effectively provides but a single usable output for each pair of input pulses.

The foregoing objects and advantages as well as the foregoing operation of my device, will be more readily seen from the following description and drawings, in which:

Figure l is a diagram of an idealized hysteresis loop of material which may preferably be used to form the core of my binary counter.

Figure 2 is a simple schematic of a binary counter op erating in accordance with the principles of the present invention, and utilized in conjunction with a low impedance input source.

Figures 3a and 3b are respectively wave form diagrams of input pulses which are applied to my counting device, and of blocking pulses which may be employed in one form of my device.

Figure 4 is a simple schematic of a single core binary counter in accordance with my invention, which utilizes blocking pulses and a relatively high impedance input source; and

t a still further embodiment of my single core binary counter which may be utilize-d in connection y high impedance source without requiring blocking pulses.

Referring now to Figure l of the drawings, it will be seen that an idealized hysteresis loop of material which may be used as the core member, for the single core binary counter of the present invention, defines a substantially rectangular form. Materials exhibiting this from the following discussion, such magnetic materials sis loop core after the magnetizing force has been reduced to zero. Point 11 represents an intermediate point of operation between the +Br point 10, and point 12 which isthe point of positive saturation (-I-Bs). The lower part of the curve represents or presents similar points, namely, points 13 (Br or minus remanence), point 14 (-Bs or minus saturation), and point 15 which correis initially at point ill, namely, at plus remanence, and a voltage is applied to the coil tending to produce a current in a direction of +H, thereby to increase the flux through the said core to point +Bs (point 12), the coil exhibits a relatively low impedance and a large current will pass through the said coil under these conditions of operation. On the other hand, if the core was initially at an operating point such as 13, or minus remanence, a voltage pulse tending to produce a current of the same polarity (-j-H) as was previously applied to the said coil must now drive the core from -Br through +Hc to the region of point 11, and during such a traverse of the hysteresis loop, the coil exhibits a relatively high impedance. In this latter circumstance, only a small current will pass through the said coil. Thus, in summary, it will be seen that if the core is initially at +Br a coil thereon will exhibit a relatively low impedance to a voltage tending to drive that coil to +Bs, while on the other hand, if the core should initially be at -Br a coil thereon will exhibit a relatively high impedance to a like voltage tending to drive the core to +Bs. These operating characteristics become quite significant and of great value in the construction of the very simple counter of the present invention.

Referring now to Figure 2, it will be seen that I provide in the basic form of counter shown therein, a core 24 of material preferably exhibiting a hysteresis loop such as is shown in Figure l. The core material may be made of a variety of materials, among which are various types of ferrites, and various kinds of magnetic tapes, including Orthonik and 4-79 Moly-Permalloy. These materials may have different heat treatments to give them difierent properties. In addition to the wide variety of materials applicable, the cores of the counter devices such as will be shown here, may be constructed in a number of different geometries incolving both closed and open paths. For example, cup-shaped cores, or strips of material, or toroidal cores are possible. For ease of description, the present invention has shown but a simple bar core. The bar core shown may be regarded a san edge view of a toroidal core. This is by no means limitative of the cores which may in fact be used, however. It is therefore to be understood that the present invention is not limited to any specific geometries of the core nor in fact to any specific materials therefor. It is preferable that the materials possess a hysteresis loop approaching the idealized hysteresis loop shown in Figure l, but this is by no means necessary, and many other hysteresis loop materials will operate in substantially the same way and effect most desirable results.

Returning now to the circuit shown in Figure 2, it will be seen that a coil 21 is wound upon the core 20, in the direction shown. If an input voltage pulse should be applied to the terminal 22, and if this input pulse is positive going in nature (-l-H), it will tend to establish a flux in the direction of the solid arrow shown above coil 2%. On the other hand, if the coil should carry a current in a direction opposite to that of the input pulse previously described (i. e. -H), a flux in the direction of the dotted arrow will tend to become established. If it should now be assumed that the core 20 is at point 10 of the hysteresis loop shown in Figure l, namely, at plus remanence, an input pulse, such as is shown at Figure 3a and having a pulse length of t-l to t2, will tend to drive the core 24) from point It) to point 12, namely, from plus remanence to plus positive saturation. During such operation, the coil 21 exhibits a relatively low impedance and the energy of the input pulse shown in Figure 3a will pass for the most part through the said coil 2i. Coupled. to the lower end of coil 21 is a parallel combination of capacitor C and load resistance Rn, which parallel combination is grounded at point 23. Again, an output point 24 is provided from the top of load resistor R1... As a result of this configuration, the input pulse A, shown in Figure 3a, will cause the capacitor to be charged during the time of application of the said input pulse. The actual charging path is from point 22 through coil 21 to the parallel combination of C and RL, and the capacitor charge rises more or less on an exponential for at least some combinations of circuit parameters. Although the actual charge configuration has not been shown, it will readily be obvious to those skilled in the art that at the end of the pulse time tl to t2, capacitor C will have a significant charge thereon. During this input time t-l to t2, an output will appear across R1. which output may be taken from terminals 24. At the end of the t1 to t2 period, the input pulse A ceases,

and capacitor C will tend to discharge. The discharge paths at this time are the parallel paths of (a) Rn to ground (thus maintaining this output for a short time) and (b) the coil 21 in a direction reverse to that of the charging path. As a result of this latter operation, it will be seen that the discharge of capacitor C will cause a current to flow in the coil 21 in a direction (-H) opposite to that of current flow caused by input pulse A. The portion of the capacitor C discharge current passing back through the said winding 21 is suiiicient to drive the core from +Br back along the loop in a counterclockwise direction past -He to at least the region of point 15 (Figure 1). Upon discharge of the capacitor which discharge is substantially completed before time t3, the core will ride back along the loop to point 13 or minus remanence preparatory to the reception of the next input pulse B (shown in Figure 3a). Thus, at time T3, core 29 is at point 13, as shown in Figure l, and input pulse l3 having a pulse length of :'3 to t4 will be required to fiip the core from point 13, or minus remanence, to the region of point 11. During this traverse from minus remanence to plus saturation, or more truly to the region of point 11, the coil 2ft exhibits a relatively high impedance and as a result the great majority of energy in pulse B is expended in the flipping of the core rather than in passing energy to the load resistor RL. During the pulse time 3 to t4, when the pulse input is removed, the core 2% is once more at point 10 or plus remanence preparatory to the reception of a third input pulse such as pulses A and B, shown in Figure 3a. In short therefore because of the configuration of core 29, winding 21, capacitor C and load resistor RL, an output is obtained for the first input pulse A and practically no output is obtained for the second input pulse B. At the end of the second input pulse B, the core is in the same state it was at time rl, and the cycle of operation can be repeated. Thus only one major output is obtained for two successive input pulses. This operation thus conforms to the necessary requirement of a binary counter and such a binary counter may be employed in any application wherein such a characteristic of operation is desired. It should further be noted that output pulses across Rr, may, by the use of appropriate circuit means, be strictly limited to either the period of charge or of discharge of C.

As has been discussed, one of the discharge paths for capacitor C is back through coil 21 to the input source. This necessitates a so-called low impedance source, but this terminology has been used generically to denote any source which is capable of accepting a reverse current at its output terminals. It often occurs, however, that such a source is not available or that a counter is required to be coupled to a so-called high impedance input source (or more exactly, one which cannot receive reverse current at its output terminals). If such a circumstance should arise, the counter configuration shown in Figure 4 is a practicable solution. Again, this counter comprises a core 40 bearing a single coil 41 thereon, the lower end of which is coupled to the parallel combination of C and R1,, described previously. In this respect, the configuration of the circuitry shown in Figure 4 is precisely the same as that shown in Figure 2. The input pulses, of the type shown in Figure 3a, are applied at input terminal 42 which designates an input source having a relatively high impedance or a source which is not capable of receiving a reverse current. One example of the type of supply coupled to terminal 42 is the typical voltage regulated power supply. In this respect, for instance, it should be noted that such a voltage regulated power supply is normally so constructed that the output terminals cannot readily receive current put into them. The input pulses of Figure 3a are fed through a diode D-1, to point 43, representing the upper terminal of coil 41 and these pulses pass down through the coil to charge capacitor C in substantially the same manner described in reference to Figure 2. Also coupled to the point 43 is a blocking pulse source 44 of relatively low impedance having a diode D2 interposed between the source 44 and point 43. Blocking pulses, which are applied to terminal 44 are of the form shown in Figure 3b and, as may be seen from the said Figure 3b, these pulses are positive going in character, having a magnitude of (E -fiE). Thus, inasmuch as the blocking pulse is applied in phase with the input pulse of Figure 3a, and further inasmuch as the blocking pulse is in magnitude larger than the input pulse by the amount 6E, no current flow caused by the input pulse at terminal 42 will pass through diode D2. At the end of time t2, capacitor C will tend to discharge back through coil 41 to thereby flip the core to Br, as was previously described. In this case, the discharge paths are again (a) through Rn to ground and (b) through coil 41 to point 43. From point 43, however, discharge current passes through D2 to the blocking pulse source 44; thus the discharge paths or a portion thereof at least has been changed to take into account the fact that input source 42 could not receive these discharge currents. The blocking pulse source is, as has been mentioned previously, normally chosen to be a low impedance source. Further, a single source of blocking pulses may serve a plurality of counters of the type described.

To summarize once more, the circuit of Figure 4 operates much like that of Figure 2, in that, assuming the core to initially be at +Br or point 10, the first input pulse finds a relatively low impedance presented by the coil 41 whereupon relatively high current flows through the said coil 41 to charge capacitor C and to give an output across RL. During the time period 12 to t3, core C is fipped down to point 13 or minus remanence by the reverse current discharge of capacitor C. During the next period, t3 through t4, input pulse B finds a relatively high impedance presented by coil 41, whereupon only a very small current can pass therethrough to the parallel combination of C and RL. The charge received by capacitor C during this period t3 to r4, is not suflicient to flip the core back to Bs during the period t4 to 15, but only to the point 11 and thence to plus remanence at point 10, whereupon the third input pulse will again give another output. Thus, once more, only a single output is obtained for two input pulses.

It should be noted in passing that, while Figure 3 appears to show the time periods t-lt2, 12-13, etc. to be equal, as an actual matter they need not be and, in general, are not in fact equal. The only requirement is that the volt-second area, e. g. E(t2rl) shall be, for a given device, a constant. The time 12-13, for example, can be any value if it is at least long enough to permit the discharge of the capacitor.

It is often inconvenient to provide a separate blocking pulse source and this situation is once more often coupled with a requirement that the input pulse source be of a type incapable of receiving a reverse current flow, e. g. a non-linear driver or a high impedance source. Under such circumstances, an arrangement such as is shown in Figure may be employed. The binary counter of this figure again utilizes a core 50 having a single coil 51 wound thereon to the lower end of which is connected the parallel combination of C and R1,, previously discussed. The input pulses are once more as shown in Figure 3a and they are again received at an input terminal 52 representing a source incapable of receiving a reverse current flow at its output terminals. Again, a diode D4. is interposed between the said terminal 52 and point 53 representing the top of coil 51, and a resistance R is also connected between point 53 and ground. Inasmuch as the circuit of Figure 5 may be used where the input source has the ability to supply a large current (i. e. has a low output impedance) but is incapable of accepting a reverse current flow, the resistor R is connected as shown rather than simply being connected from terminal 52 to ground.

The resistance R is preferably chosen to exhibit an impedance having a magnitude intermediate the high and low impedances presented by coil 51 at its two main operating conditions discussed previously. During the time tl to t2, a voltage pulse input causes a current to pass through the diode D4, thence through coil 51 to the parallel combination of C and RL. A portion of this current also passes through resistor R to ground. Because of the value of resistor R as compared to the low impedance value of coil 51 at this time, however, the applied input pulse causes a relatively large current to pass through the said coil 51 to capacitor C and resistor R1,, thereby to charge the capacitor as previously described. Again, from time t2 to :3, capacitor C discharges through the parallel paths of (:1) RL to ground, thus maintaining the output for a time; and (b) back through coil 51, and resistor R to ground. Thus, the charge and discharge paths are substantially the same as those discussed in reference to Figure 4. it should be noted that when the configuration of Figure 5 is utilized, auxiliary outputs may be obtained across resistor R. While I have described the resistor R as assuming an impedance intermediate that of the high and low impedance points of coil 51, this is by no means mandatory and any value of impedance within limts may be chosen to efiect any desired pulse characteristics across the re sistor R.

As may be seen from the foregoing, simple binary pulse counter has been provided which utilizes in eifect but a single magnetic core having a winding thereon, to one end of which Winding is coupled a capacitor having differing charge and discharge paths. The essential characteristic of these paths is that the winding provides a portion of both the charge and discharge paths, and the discharge current, which is in a direction opposite to that of the charging current, is of suflicient magnitude to flip the core from one remanent point to another remanent point, thereby to effect a major change in the impedance of the coil wound on the said core. The several input pulses are, of course, selectively applied. In additon, it must be emphasized that once the core is at one or another of its remanent points, no power is required to maintain the said core at that particular operating point. Further, while I have described the output as occurring when the core is driven from +Br to +Bs, the circuit could also be arranged so that the output occurs during operation from Br to Bs.

While I have described but a simple form of my invention, other modifications will readily suggest themselves to those skilled in the art; and it is to be stressed that the foregoing illustrations are not meant to be limitative of my invention, but are truly illustrative only. Thus, for instance, the core may carry two coils thereon, each of which coils has one end coupled to a common resistorcapacitor network of the type already described. By coupling suitably poled buflers to the other ends of said coils (and by applying blocking pulses to one of said buffers during the application of input voltage pulses to the other of said buffers) the capacitor may be caused to charge through only one of said coils and to discharge only through the other of said coils. With such an arrangement, certain advantages may be derived by proper choice of the number of turns on each of said coils. Thus, if the number of turns on the discharge coil is less than the number of turns on the charge coil, more effective flipping will be obtained from the discharge current since the flipping voltage varies directly with the number of turns on the coil carrying flipping current. Other modifications will also be apparent to those skilled in the art.

Having thus described my invention, I claim to have invented:

1. A binary counter comprising a core of magnetic material exhibiting a substantially rectangular hysteresis loop, a coil wound on the said core, a source of input pulses coupled to one end of said coil, and a capacitor therefore, a very coupled to the other end of said coil, whereby said capacitor is selectively charged through said coil by said input pulses and said capacitor passes a reverse discharge current through said coil between successive ones of said input pulses thereby to change selectively the operating point of said core on said hysteresis loop.

2. A binary counter comprising a core of magnetic material exhibiting a substantially rectangular hysteresis loop, a coil wound on the said core, a source of spaced input pulses coupled to one end of said coil, said coil being so wound on said core that it exhibits a relatively low impedance to said input pulses when said core is at one of its remanence points, and exhibits a relatively high impedance to said input pulses when said core is at the other of its remanence points, energy storage means coupled to the other end of said coil, whereby a first input pulse coupled to said coil when said core is at said one point of remanence effects a significant storage ct energy in said storage means, the stored energy in satd storage means causing a reverse current to flow through said coil after completion of said first input pulse thereby to flip said core to the other of its remanence points preparatory to reception of a second of said input pulses.

3. The counter of claim 2 in which said source of input; pulses is so constructed that it is capable of receiving a reverse current at its output terminals whereby the reverse current flow efiected by said storage means passes to said source of input pulses.

4. The counter of claim 3 in which said charge storage means comprises a capacitor in parallel with a load irnpedance, whereby a portion of said reverse current passes to said load impedance thereby to effect a selective output from said binary counter.

5. The counter of claim 2 in which said source of input. pulses is so constructed that it is incapable of receiving a reverse current at its output terminals, buffer means interposed between said source of input pulses and said one end of said coil to permit current flow in a single direction only, a source of blocking pulses, and further butler means coupling said source of blocking pulses to said one end or" said coil.

6 The c t: ter of claim 5 in which said bloclai "-3 source is capable of receiving a reverse current at its output terminals, said further buffer means being so poled that current may flow from said one end of said coil to said source of blocking pulses.

7. The counter of claim 6 in which said blocking pulses and said i put pulses are in phase with one another, the magnitud of said blocking pulses being such that said further bunjcr means is cut ofif during application of said input pulses.

8. The counter of claim 2 in which said source of input pulses is so constructed that it is incapable receiving a reverse current at its output terminals, butter means interposed between said source of input pulses and said one end of .id coil, an impedance, and coupling said one end of said coil to said impedance.

References Cited in the file of this patent UNITED STATES PATENTS l,75l,263 Cesareo Mar. l8, 1930 

